Gidel designs and manufactures industrial machine vision image acquisition frame grabbers, range extenders, camera simulators, IP cores, and application development kits and tools. Gidel also provides custom machine vision and FPGA programming and development services.
Gidel has 25 years experience developing high-end FPGA systems as products, such as PCIe accelerator boards, for sale or as integration projects for customers. Gidel’s advanced development tool kit ensures fast, high quality outcomes, and is also available to end-customers to purchase.
Gidel has 25 years experience developing high-end FPGA systems as products for sale or as integration projects for customers using a combination of industry standard tools such as OpenCl, and internal advanced development tools, which are also available to end-customers.
Gidel products, tools, and expertise are used in applications including security, DNA research, machine learning, imaging and vision systems, augmented and virtual reality, deep learning, and reconfigurable interconnect frameworks for HPC clusters.
An intelligent FPGA solution for high performance FPGA acceleration from Gidel requires speed, compute efficiency, and best use of memory capacity and bandwidth.
Gidel has the knowledge, experience, and has developed extremely stable tools based on the latest technology to reduce development time and effort and to ensure long product life cycles.
Zerif Technologies Ltd. of London, England, provides advanced electronics products for science and industry, and is an international distributor for Gidel. Zerif is a wholly owned subsidiary of Sky Blue Microsystems GmbH of Munich, Germany, founded in 1999.
Gidel adds frame grabber functionality to its powerful range of PCIe FPGA boards, with suitable IP and connectors to support CoaXPress CXP1 at 6G and CXP2 at 12G, Camera Link, 10GigE Vision, and proprietary fiber via SPF transceiver cages. These world-class products have been well-received by customers worldwide, and deliver extraordinary performance and stability.
Gidel image acquisition frame grabbers come in the PCIe form factor running Gen3 and using 1 through 16 lanes. Gidel also make a MIPI frame grabber.
Between one and eight device links can be attached to a single frame grabber, and parallel cards synchronize frames in a single frame for further processing by the CPU or GPU.
Camera Link distance limitations are solved without repeaters using fiber optic range extenders. Range extenders can also serve as an optical isolator in industrial machine vision systems. At the host side, the fiber optic cable from the Gidel RCLF can be attached directly to a frame grabber without CameraLink conversion.
The Gidel CamSim generates video streams and test patterns, or serves image data from a user source. These machine vision camera simulators are used in the development, testing, and debugging of systems and components, including cameras, frame grabbers, and software.
The Gidel JPEG Compression IP Core and Lossless Compression IP Core are ultra-high-speed and high-efficiency, stable, reliable Intellectual Property for embodiment in your systems.
Gidel has been developing FPGA solutions for over a quarter of a century, and can share that knowledge, skill, and experience with customers to produce your desired machine vision or other custom IP. Algorithms can be modified or added in the frame grabber FPGA and software. The existing Gidel frame grabber IP Core is available for the user to amend and enhance with embedded user-defined algorithms. The Gidel “ProcWizard” dev kit tool suite aids development and amendment of IP, as does “ProcVision” for machine vision IP core development and customization.
Gidel’s Total History IP Core is an innovative signal tracing tool for FPGA prototyping enabling virtually unlimited signal trace depth, and massive and flexible probing of real system performance. TotalHistory uses the unused on-board memory and memory bandwidth of the FPGA boards, thus requires no additional resources.
GiDEL’s novel TotalHistory IP opens the way to unprecedented design visibility. TotalHistory is based on a unique design-embedded IP core. Probes are inserted at any design point of interest to capture signals at full operating speed; signal trace is stored in the on-board memory or on peripheral SODIMMs at practically unlimited depth (up to 8.5 GB/FPGA) enabling virtually infinite signal tracing regression to accurately detect, reproduce, and isolate system bugs. Real-time signals are channeled to the host allowing user application processing to generate complex triggering schemes to detect bugs and to capture vital internal signal states. Once a trigger is issued, virtually infinite signal trace history can be retroactively analyzed by the host application, or by a simulator via the PCI/e bridge, or via Gigabit Ethernet (in the case of a PROC_SoCTM system). TotalHistory can support as much as 100,000 fully configurable probes per FPGA permitting comprehensive signal visibility.
Gidel’s InfiniVision technology allows development of Augmented and Virtual Reality products to utilise high quality image content from a large camera arrays to generate 360 degree panoramas for the latest immersive entertainment and sports experiences.
Gidel’s low-latency, full duplex direct FPGA connectivity technology allows customers to build Reconfigurable Interconnect Frameworks for HPC clusters with no CPU overhead. 3D and 12D Torus and 6D and 24D Hypercube topologies can be optimized to become the HPC infrastructure required for compute-intensive workloads.
The Gidel Developer’s Suite is based on 25 years of continuous improvement. Developer’s Suite gives you unmatched development productivity. The Gidel Developer’s Suite consists of:
Proc Developer’s Kit (ProcDev Kit), as an alternative to existing FPGA design methodologies. It is oriented towards implementing your algorithms in a user friendly and efficient manner.
HLS Application Support Package (I++) allows you to use Intel’s High Level Synthesis (HLS) tool, which generates Register Transfer Level (RTL) from C++ input. The output is optimized for FPGAs.
Gidel supports Intel’s Open Vino Artificial Intelligence and Machine Learning libraries.
Gidel supports Halcom’s MVTec comprehensive standard software for machine vision applications.
Gidel provides OpenCL Board Support Packages (BSPs) for FPGA compute accelerating.
The Gidel Proc10S high performance scalable compute acceleration board is powered by an Intel Stratix 10 FPGA with up to 200 Kle, 260 GB DDR4 RAM, and an option for a SoC Quad-core 64-bit ARM Cortex-A53 MPCore processor. Peak single precision performance reaches 10 TFLOPS.More…
Gidel’s Proc10M module is designed to enable easy use and immediate accessibility to the powerful Intel Stratix 10 FPGA with HBM2 on-chip memory technology for both host and embedded systems.More…
The Proc10A™ system is a flexible, high performance, low-power FPGA platform based on Intel’s powerful Arria 10 FPGA. The Proc10A offers high I/O throughput and high powered on-board processing and data management for low latency for applications such as HPC high performance computing, storage, networking, and high-end imaging.More…
The HawkEye is a PCIe 8 lane Gen 3 low profile board based on Intel’s Arria 10 FPGA. This compute accelerator has up to 18 GB DDR4 on-board memory, up to four SFP+ links for a maximum of 56 Gbs. The Arria 10 FPGA provides up to 480K LEs and IEEE floating-point numbers.More…
Gidel offers a number of ultra-compact high-performance FPGA modules that can be mounted on a PCIe carrier board. The modules provide a complete FPGA envelope ready for use while leaving flexibility to tailoring the peripheral system precisely. Gidel provides templates and powerful development tools that enable quick development and optimal FPGA utilization.More…
The Gidel Proc Developer’s Kit (ProcDev Kit) is an easy to use FPGA design tool. It optimises on-board memory and host communication in support of your algorithm implementation on the FPGA. The Developer’s kit includes the ProcWizard application, an API, Gidel IPs, examples, and HDL and software libraries.More…