FPGA Main Board Accelerators

The BittWare 520C is a PCIe accelerating OpenCL-programmable FPGA board built using the Intel Stratix 10 with F1760 NF43 package and a PCIe Gen3 x16 host interface. With fast, independent optical I/O, establish dense, directly coupled FPGA clusters.

The BittWare 520N is a PCIe accelerating OpenCL-programmable board built using the Intel Stratix 10 F1760 NF43 FPGA with four 100G QSFP Ethernet ports and a PCIe Gen3 x16 host interface. With fast, independent optical I/O, establish dense, directly coupled FPGA clusters.

The BittWare 520N-MX accelerator board built with an Intel Stratix 10 MX FPGA is well suited to 100G line rate network packet processing and compute-intensive data center applications that demand high memory bandwidths.

The BittWare 385A is a low profile 1.5 Teraflops FPGA accelerator board built on the Altera Arria 10 1150 GX. It features dual QSFP ports, 8GB DDR3 SDRAM external memory, and 8-Lane PCI-Express Gen 3.

BittWare’s 385A-SFP is an Intel Arria 10 based FPGA network accelerator card for 8 lane, single width, PCI Express Gen 3, with six SFP+ ports, rated at 10 Gbps.

The BittWare 385-SoC is an ARM-based System-on-Chip FPGA accelerator board built on the Altera Arria 10 SX F34. It features dual QSFP ports, two banks of 4G DDR4 SDRAM external memory, and 8-Lane PCI-Express Gen 3 in a NIC form factor.

The BittWare 510T Compute Acceleration Card is an FPGA co-processor that delivers maximum performance-per-watt for intensive compute applications such as the datacenter. In a GPU format, and with a 16-lane PCIe Gen 3 card, it is powered by dual Altera Arria 10 floating point FPGAs. 

BittWare’s A10PL4 is a low-profile PCIe x8 card based on the Altera Arria 10 GX FPGA. The Arria 10 features high density and a power-efficient FPGA fabric. Included are high-speed transceivers, hard floating-point DSP blocks, and embedded PCIe x8 Gen3.

The BittWare A10SA4 PCIe accelerator board built with a Altera Arria 10 GX 1150 FPGA is well suited to large FPGA loads in the data center. The A10SA4 supports the Open Computing Language (OpenCL™) programming model, which enables a high-level software-like development flow, which greatly simplifies FPGA development. 

BittWare 250-SoC system-on-a-chip exploits the NVMe-over-Fabric (NVMEoF) technology of the Xilinx Zynq UltraScale+ MPSoC FPGA. It also has 64-bit ARM processors.

The BittWare 250-U2 is a proxy in-line accelerator (PIA) in the U2 form factor. FPGAs enable accelerated computing, network, and database access.

The BittWare 250S+ is powered by a Xilinx KU15P Ultrascale FPGA (FFVA1156 in default configuration speed grade 2). It is a fully programmable, flash SSD, near-storage, localized FPGA accelerator with up to 4 M.2 NVMe SSDs or M.2 to U.2 SSD Cables and DDR4 or MRAM.

The BittWare XUPP3R PCIe accelerator board built with a Xilinx UltraScale+  FPGA is designed for high-performance, high-bandwidth, and reduced latency applications demanding massive data flow and packet processing. 

The BittWare XUPPL4 PCIe accelerator board built with a Xilinx UltraScale+  FPGA is designed for high-performance, high-bandwidth, and reduced latency applications demanding massive data flow and packet processing.

The BittWare XUPVV4 PCIe accelerator board built with a Xilinx UltraScale+  FPGA is designed for high-density datacenter applications. The UltraScale+ VU13P offers up to 3.8 million logic elements.

The BittWare XUPVV8 PCIe accelerator board built with a Xilinx UltraScale+ VU13P FPGA is well suited to high density applications. The UltraScale+ VU13P offers up to 3.8 million logic elements. This power density makes thermal management difficult, but Bittware solves this problem  with the Viper platform.

The BittWare XUPVVH PCIe accelerator board built with a Xilinx UltraScale+ VU35P/37P FPGA is well suited to high density data center applications that demand high memory bandwidths.

The BittWare XUPVVP PCIe accelerator board built with a Xilinx UltraScale+ FPGA is designed for ultra high power applications. The UltraScale+ VU13P offers up to 3.8 million logic elements.

The EDT PCIe8g3 KU-10G supports PCI Express – PCIe, Gen3 - x8 and has a 40G QSFP+ and two 10G SFP/+ ports. Supported protocols are 1/10GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. Each port links to the SERDES user-interface for serialization and deserialization, and clock recovery. Each port has its own 10 – 210 MHz programmable reference clock.

The PCIe8g3 KU-10G supports PCI Express – PCIe, Gen3 x8 and has four 10G SFP/+ ports. Supported protocols are 1/10 GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. Each port links to the SERDES user-interface for serialization and deserialization, and clock recovery. Each port has its own 10 – 210 MHz programmable reference clock.

The EDT ECL / LVDS-E / RS-422-E is a mezzanine board that pairs with an EDT main board for PCI Express for high-speed data transfer. This “E-series” board options are ECL, LVDS or RS-422 inputs and outputs in groups of four, with an E1/T1 option.

The EDT PCIe4 CDa is a PCI Express 4-lane interface that enables fast DMA and synchronous I/O to transfer differential data between an external device and a host computer, LVDS or RS422. FPGA is Altera Arria II GX (EP2AGX45D) combining PCIe DMA at 700 Mbs with UI functionality at 150 Mbs I/O, which is via integrated FIFO buffers.

The EDT PCIe8g3 S5-40G supports PCI Express – PCIe, Gen3 - x8 and has one 40G QSFP+ and supports 1/10/40 GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. The ports link to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 10 – 210 MHz programmable reference clock.

The EDT PCIe8g3 S5-10G supports PCI Express – PCIe, Gen3 - x8 and has four 10G SFP+ and 1 – 10 GbE or OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. The ports link to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 10 – 210 MHz programmable reference clock.

The EDT PCIe8g3 A5-40G supports PCI Express – PCIe, Gen3 - x8 and has a 40G QSFP+ and 40 GbE or OTU3. The board is available as half-height or full-height. The port links to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 1 – 808 MHz programmable reference clock.

The EDT PCIe8g3 A5-10G supports PCI Express – PCIe, Gen3 - x8 and has two 10G SFP+ and 1 – 10 GbE or OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. This low-profile board is available as a half-height or full-height backpanel. The port links to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 1 – 808 MHz programmable reference clock.

EDT Bridge, Backpanel, and Time Boards attache to EDT main boards.