EDT PCIe8 DVa CLS Camera Link – Zerif Technologies Ltd.

EDT PCIe8 DVa CLS Camera Link simulator / framegrabber

The PCIe8 DVa CLS Camera Link simulator can be converted to a PCIe8 framegrabber with a firmware flash. Using an easy interface, a text-based configuration script defines the camera timing to be simulated. The board simulates image data so that applications can be debugged, or tested at system level when a camera is attached.

Images are transmitted via DMA from the host PC: the board has no frame buffer memory. Alternatively, internal counters can be used as the image source.

UART commands can be programmed from the C libraries. Triggering of line and frame are via camera control lines.

PCI Express bus required, 16 or 8 lanes not used for display (or an 8-lane physical slot wired as a 4-lane with reduced maximum performance). Windows and Linux software included, others on request.

This product is discontinued, but is still supported. Next-gen replacement coming soon.

This board supersedes the PCIe8 DV CLS. But is backwards compatible with the legacy board. DV applications will work with the DVa version without modification.

Product Data

PCIe8 DVa CLS Camera Link by Engineering Design Team operates in simulator or framegrabber mode supports 8 / 16-lane PCIe slots and 20 – 85 MHz pixel clock rate.
EDT PCIe8 DVa CLS Camera Link simulator / framegrabber: 8-lane or 16-lane PCIe slots and 20 – 85 MHz pixel clock rate.