Gidel has introduced an ultra-compact FPGA daughter board (FDB) incorporating Intel Arria 10 FPGAs (models 160, 270, 480 and 660), the smallest mid-range FPGAs available.
DRAM performance is up to 10 GB @ 24 GB/s, and 12 x up to 14.2 Gb/s transceivers (2 are Rx only).
The FDB modules are supported by Gidel’s DRAM controller that enables splitting the physical DRAMs into up to 16 separate logical memories, all operating in parallel, and accessing each logical memory simultaneously by multiple sequential ports, each with its own clock and data width. For example, a 128 MB FIFO may be automatically generated by Gidel’s tools utilizing a 128 MB logical memory with a single write port and a single read port.
To reduce risk, development time, and time-to-deployment, the FDB modules are supported by state-of-the-art development tools and a PCIe carrier board enabling an immediate start to application development and FPGA code. For example, a user may start developing an image processing IP using a streaming input from files and sending the IP output to a grabber for display, storage, analyzing, etc.
These daughterboards are ideal for custom PCIe or stand- alone, size-constrained systems. Applications include embedded systems and compact broadcast and image processing solutions that require grabbing data from multiple fast edge sensors then performing image enhancements, processing and compression.
The FDB modules have been designed for use with carrier boards to enable tailoring solutions to reduce risks, costs and time to market. User carrier boards may incorporate any combination of I/Os and configuration schemes. Gidel offers a PCIe developer’s carrier board allowing FPGA designers to immediately begin developing their application and proprietary FPGA design.
The Gidel development toolkit environment (“Proc Dev” and “ProcVision”) enables immediate mapping of board resources to the application, including tailored host interface and dividing the DRAM into application logical memory units by automatically generating an ASP (Application Support Package) optimized to the system requirements. It also allows tailoring high-end grabber and imaging acceleration flow in an intuitive and simple manner by customizing the ASP, software and the FPGA design code. Parallel access of multiple applications on the module FPGA expedites the development and improves system reliability. For example, firewall and compression may be accelerated simultaneously on the same FPGA and controlled by independent applications.
Please use our FPGA Board Selector to find your preferred model.