Stratix IV, Stratix V, and Arria V

The EDT ECL / LVDS-E / RS-422-E is a mezzanine board that pairs with an EDT main board for PCI Express for high-speed data transfer. This “E-series” board options are ECL, LVDS or RS-422 inputs and outputs in groups of four, with an E1/T1 option.

The EDT PCIe4 CDa is a PCI Express 4-lane interface that enables fast DMA and synchronous I/O to transfer differential data between an external device and a host computer, LVDS or RS422. FPGA is Intel Arria II GX (EP2AGX45D) combining PCIe DMA at 700 Mbs with UI functionality at 150 Mbs I/O, which is via integrated FIFO buffers.

The EDT PCIe8g3 S5-40G supports PCI Express – PCIe, Gen3 - x8 and has one 40G QSFP+ and supports 1/10/40 GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. The ports link to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 10 – 210 MHz programmable reference clock.

The EDT PCIe8g3 S5-10G supports PCI Express – PCIe, Gen3 - x8 and has four 10G SFP+ and 1 – 10 GbE or OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. The ports link to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 10 – 210 MHz programmable reference clock.

The EDT PCIe8g3 A5-10G supports PCI Express – PCIe, Gen3 - x8 and has two 10G SFP+ and 1 – 10 GbE or OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. This low-profile board is available as a half-height or full-height backpanel. The port links to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 1 – 808 MHz programmable reference clock.

EDT Bridge, Backpanel, and Time Boards attache to EDT main boards.