The EDT PCIe8g3 S5-10G supports PCI Express – PCIe, Gen3 - x8 and has four 10G SFP+ and 1 – 10 GbE or OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. The ports link to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 10 – 210 MHz programmable reference clock. The UI FPGA is a Altera Stratix V GX (A3, A5, A7, or A9) with access to two DDR3 DRAM, 4 GB 64-bit, that is also a buffer. The PCIe FPGA provides up to 16 independent DMA channels via EDT FPGA configuration files. An optional Lemo supports 1 pps or IRIG-B) time codes, with either DB9 or BNC. Configuration files support 1 and 10 GbE at PHY, and OC3/12/48/192 and OTU1/2/2e/2f – raw, framed, framed and descramble.
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