The EDT PCIe4 CDa is a PCI Express 4-lane interface that enables fast DMA and synchronous I/O to transfer differential data between an external device and a host computer, LVDS or RS422. FPGA is Altera Arria II GX (EP2AGX45D) combining PCIe DMA at 700 Mbs with UI functionality at 150 Mbs I/O, which is via integrated FIFO buffers. Configuration is either standard DMA: with one 16- or 32-bit parallel channel, or 16 synchronous serial channels; or low-latency DMA with one 16-bit parallel channel; or 1 parallel channel, at 600 MB/s total for 32-bit, or 300 MB/s total for 16-bit; or 1 serial channel at 150 Mb/s. Data and control signals are sampled by a synchronous clock protocol, generated by the DMA interface, the user device, or both. Access to the source VHDL is available.